Non-Volatile Memory (“NVM”) cells come in a variety of cell structure, including “Floating Gate” and “Nitride Read Only Memory” (“NROM”). NVM cells generally are formed of transistors with programmable threshold voltages. The transistors have a threshold voltage (“Vt”) that is programmed or erased by charging or discharging a charge storage region located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the charge storage region of the memory cell, so as to achieve threshold voltages corresponding to the data. An NVM cell may either be adapted to store a single bit in a single charge storage region, multiple bits in multiple charge storage regions, or multiple bits using multiple level programming (“MLC”), either in a single or in multiple charge storage regions.
A group of NVM cells may be configured in a variety of array structures, generally having a grid of columns and rows with at least one cell at each intersection. Various NVM array structures may be operated in different modes of operation. For example, NVM cells may be formed and operated as, but not limited to, erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memory arrays.
Arrays of NVM cells are typically fabricated on a semiconductor substrate adjacent to circuitry adapted to program and read data to and form the array. The programming and reading circuitry may be generically referred to as a controller of coder/decoder. The controller typically has interface lines allowing it to interconnect with applications or digital devices requiring access to the NVM array. Various controllers conform to various standards for communication with outside applications or digital devices, for example the controller may be adapted to communicate using the SmartCard or MMC standards.
Since NVM based devices have a certain probability of bit read or write errors when being operated, controllers may include “Error Detection” and/or “Error Correction Coding” (“ECC”) functionality. NVM chips or devices with built-in error-checking typically use a method known as parity to check for errors. The problem with parity is that it discovers errors but does nothing to correct them. Critical application may need a higher level of fault tolerance, and thus when storing data on an NVM array, controllers may produce an ECC associated with the data being stored and may store the ECC along with the original data. When reading the data from the array, the controller may use the data's associated ECC to recover data lost because of errors produced when either programming or reading the data.
A controller may also include a memory buffer to temporally store data as it is being written to, or read from, the NVM array. Data to be stored on an NVM array may first be stored on the memory buffer, along with the data's associated ECC. Each slice of the memory buffer may be copied to a portion of a row in the NVM array.
In memory arrays composed of dual or multi-charge storage region cells and/or MLCs, where multiple bits may be stored on a single cell, two or more adjacent bits in a slice of the memory buffer may be copied onto a single memory cell on the NVM array. Storage of multiple adjacent bits from a data stream or data block on a single NVM cell may have drawbacks relating to data recovery in the event the cell fails.